7 days

It has been almost a week since I finished my finals. Friends were going off & packing stuff...ready to get home as soon as possible, while we computer engineers had to stay for our final year project or better known as FYP. This FYP alone was not as hard as I expected. But, when problems and issues comes one after another...that's when the obstacles gets tougher. First of all, I'll start off with my project titled "FPGA-based Multi Level Parking Monitoring System".

Basically, this project helps users to reduce the amount of time spent in the parking lot, searching for a car park when there isn't one. More to like assisting the users in which parking basement has available parking space. I'll opened up a new post specifically for my project later.

Emotions and all started coming in throughout the FYP week. It was the last 7 days of our diploma before we have to present our project to the panels. All I did was pushing...pushing and pushing myself so hard...with one purpose = To complete the project. Every morning, I wake up as early as 7.30am...to catch the 8.30 bus to my FYP lab. Stayed there till 5pm. If there's no transport back to the hostel, I'll just hafta walk...which I actually did.

There are times when I feel like I couldn't go on. It was tiring, frustrating, mentally stressed up trying to troubleshoot my sensor circuit for about 3-4 hours. No time to relax. Thank goodness I made it. Out of 4 sensor circuits I've soldered, only 2 managed to produce the desired output.

Infrared Transmitter & Receiver

Modeling the project

The Finale:

The day I've been waiting for throughout this whole semester is here. The VIVA demonstration of your project. This day, each and everyone of us are to show your results of your FYP. No matter how bad it goes...you just have to show something. The list of presenters are as follows;

1. Lim Foong Jien
2. Marcus Koh Eu Zu
3. Lee Yee Ann

I was 2nd on the list! Wtf!? And there's is only one FPGA board which is being used by my partner for his project. So when the panels came, I told them that we had to share one single board. One of the panels said "That's your problem!". I didn't wanna argue, so I just sighh...and told them to continue. After some discussion...they allowed me to buy some time while I fix up my project to the FPGA board. It was a sense of relieved!

Kite the 1st presenter

Me the 2nd presenter... I explain my reasons...

I fix my project as soon as I can. Sad to say that the whole system is behaving abnormally. It has to be either the circuitry of the wires, or the sensors itself. I tried to troubleshoot as much as I can. My partner's FPGA board had problems as well, so he asked whether he could use mine. As u know, my whole circuit is wired with the board...and to put them back again takes about 30mins or more.

I was in dilemma. It's the 9th presenter now, and I have tried my best trying to troubleshoot my project. They gave me more than enough time already. So, I decided to tell the panels to VIVA me after the 9th presenter. It was the only way...

Explains the project to the panels...


En. Nasir asking me about the system...

The project wasn't a failure. I could produce the perfect results the day before. I told them how the system is suffering. Bla bla bla... + confidence. I was able to answer most of the questions they throw at me...except for that one and only. He just keeps coming at me...expects me to produce a project as intelligent as the japanese or something. Other panels don't find it a problem... Anyways, I believe that they understood what I was saying.

The whole VIVA thingy ended at 8.30pm. Imagine how long we were there in the lab since 9.00am. Gila tired. Went to KFC for some good meal and chats + discussion about the whole FYP demo thingy.

Safwan and I